System Verilog 中的 RTL 有限状态机
RTL Finite State Machines in System Verilog
- 1 - Welcome to the course !
- 1 -Introduction
- 2 -Learning Tips (Optional)
- 3 -FSMs in Digital Logic
- 3 - RTL FSM Design Pattern
- 1 -RTL FSM Design Pattern
- 4 - RTL FSM Example
- 1 -RTL GCD
- 2 -State Definitions
- 3 -Transition Arcs
- 4 -RTL Simulation - 1
- 5 -RTL Simulation - 2
- 6 -Synthesis
- 5 - RTL FSM - Fewer States
- 1 -Measure Latency - 1
- 2 -Measure Latency - 2
- 3 -Fewer States
- 4 -Synthesis
- 6 - Extra Explicit One Hot Encoding
- 1 -One-Hot Encoding
- 2 -GCDOne Hot Encoded
- 3 -Simulation
- 4 -Synthesis
- 5 -Gatesim
- 7 - Wrap Up
- 1 -Wrap Up
- 8 - Docker Setup (Optional)
- 1 -Docker Windows Install (Optional)
- 2 -Download Docker Image
- 3 -Run Docker with GUI (Windows)
- 4 -Test Install
- 9 - EDA Playground Setup (Optional)
- 1 -EDA Playground Hints (Optional)